This invention relates to the operational control of a digital computer system, and more particularly, to the digital logic circuitry for temporary storing results internal to an execution unit wherein the intermediate results are to be utilized as operand data in the execution of the next instruction.
An objective, which almost always faces designers furthering the advancement of digital computers, is to decrease the time required for executing each of the instructions executed by the digital computer, thereby decreasing the overall time required by the digital computer to perform a predefined task and increasing the efficiency of the digital computer. Many schemes have been devised by digital computer designers in an attempt to meet this objective. In the execution of many instructions, the reading of stored operand data from a memory storage device must be performed. The time for reading the stored operand data may vary greatly depending on the architecture of the data processing system. In order to assist in speeding-up the fetch time, i.e., the time required to read the operand data from the memory device, recent data processing systems have incorporated the use of a cache memory. In spite of the utilization of a cache, a delay occurs when the results of a first instruction are to be used as an operand of a second instruction immediately following the first instruction. The delay, sometimes referred to as the store-load break, is caused by having to write the results to a cache (or memory) and then read the results back again into the execution unit.
Therefore, there is provided by the logic circuit of the present invention an apparatus for holding the results of an instruction execution for use in the execution of the next instruction. The apparatus of the present invention also functions as an auxiliary input stack thereby eliminating the time delay caused by requiring a (cache) memory read operation.